The present invention relates generally to a phase change memory device, and more particularly, to a phase change memory device for enhancing an operating characteristic of a main cell which includes a discharge path of a bit line and a dummy cell array.
A nonvolatile memory has a data processing speed similar to that of a volatile Random Access Memory (RAM), however, unlike a volatile RAM, a nonvolatile memory conserves a data even when no power is supplied to the memory, i.e., when the power is turned off. Examples of a nonvolatile memory include a magnetic memory and a phase change memory (PCM).
FIGS. 1a and 1b are diagrams showing a conventional phase change resistor (PCR) 4.
The PCR 4 comprises a phase change material (PCM) 2 inserted between an upper electrode 1 and a lower electrode 3. When a voltage and a current are applied to the conventional PCR 4, a high temperature is generated in the PCM 2 such that an electric conductive state of the PCR 4 is changed depending on resistance of the PCM 2. The PCM includes AgLnSbTe. The PCM 2 may comprise chalcogenide having chalcogen elements (S, Se, Te) as a main ingredient, and specifically includes a germanium antimonic tellurium consisting of Ge—Sb—Te.
FIGS. 2a and 2b are diagrams illustrating a principle of the conventional PCR 4.
As shown in FIG. 2a, the PCM 2 can be crystallized when a low current, i.e., a current less than a threshold value flows in the PCM R. As a result, the PCM2 is crystallized to be a low resistant material.
As shown in FIG. 2b, the PCM 2 can be amorphized when a is high current, i.e., a current higher than a threshold value, flows into the PCR 4. That is the temperature of the PCM 2 is increased higher than the melting point of the PCM 2 when a high current flows into the PCR 4. As a result, the PCM 2 becomes amorphous and acts as a high resistance material.
In this way, the PCR 4 is configured to store nonvolatile data corresponding to the two resistance states. Data “1” refers to a low resistance state of the PCR 4, and data “0” refers to a high resistance state of the PCR 4, and as such the data can be stored to have one of the two logic states.
FIG. 3 is a diagram showing a write operation of a conventional phase change resistant cell.
Heat is generated when a current flows through the top electrode 1 and the bottom electrode 3 of the PCR 4 for a given time. As a result, a state of the PCM 2 is changed to be either crystalline or amorphous depending on the temperature generated according to the current applied to the upper electrode 1 and the lower electrode 3.
A low temperature heating state occurs when a low current flows for a given time. As a result, the PCM 2 becomes crystalline and the PCR 4, which acts as a low resistor, is at a set state. On the other hand, a high temperature heating state occurs when a high current flows for a given time. As a result, the PCM 2 becomes amorphous and the PCR 4, which acts as a high resistor, is at a reset state. A difference between two phases is represented by a change in electric resistance.
As shown in FIG. 3, a low voltage is applied to the PCR 4 for a long period of time in order to write the set state in a write mode. On the other hand, a high voltage, which is greater than the low voltage, is applied to the PCR 4 for a shorter period of time in order to write the reset state in the write mode.
FIG. 4 is a diagram showing a cell array of a conventional phase change memory device.
The conventional cell array includes a plurality of unit cell C arranged intersections of a plurality of bit lines BL1˜BL4 and a plurality of word lines WL1˜WL4. The unit cell C includes a phase change resistor PCR and a diode D. The diode D includes a PN diode element.
The phase change resistor has one electrode connected to a bit line BL and the other electrode connected to a P-type region of the diode D. An N-type region of the diode D is connected to a word line WL.
In a read mode, a low voltage is transmitted to the selected word line WL. A read voltage Vread is transmitted to the bit line BL so that a read current Iset, having a set state, or a read current Ireset, having a reset state, flows toward the word line through the bit line BL, the phase change resistor PCR, and the diode D.
A sense amplifier S/A senses cell data applied through the bit line BL and compares the cell data with a reference voltage ref to distinguish data “1” from “0”. A reference current Iref flows in the reference voltage ref terminal. A write driving unit W/D supplies a driving voltage, which corresponds to write data to the bit line BL, when data are written in a cell.
FIG. 5 is a circuit diagram illustrating a conventional phase change memory device.
The phase change memory device includes a plurality of cell arrays CA_m, CA_n, bit line discharge switches N1˜N8 for discharging charges of the bit line BL in a precharge mode, and column switches N9˜N16. Each of the cell arrays CA_m, CA_n includes a unit cell C arranged at an intersection of the bit line BL and the word line WL.
The bit line discharge switches N1˜N8 are connected between a bit line BL and a ground voltage terminal, and are controlled by bit line discharge signals BLDIS_m, BLDIS_n. When the bit line discharge signals BLDIS_m, BLDIS_N are activated, the bit line discharge switches N1˜N8 are switched on and supply a ground voltage to the bit line BL and provide a discharge path for the bit line BL.
The column switches N9˜N16 are connected between a bit line BL and a global bit line GBL, and are controlled by column selecting signals LY1_m˜LY4_m and LY1_m˜LY4_n. The column switches N9˜N16 are selectively switched on in response to the column selecting signals LY1_m˜LY4_m and LY1_n˜LY4_n and control the connection between the bit line BL and the global bit line GBL.
In an active mode, one of the column selecting signals LY1_m˜LY4_m is activated selecting the unit cell C connected to a corresponding to the bit line BL, and one of the column selecting signal LY1_n˜LY4_n is activated selecting the unit cell C connected to a corresponding to the bit line BL.
In the conventional memory device, the bit line discharge signal BLDIS is inactivated to a low level during the active cycle. In the precharge period, the bit line discharge signal BLDIS is activated to a high level to discharge the bit line BL to a ground voltage.
The bit line discharge switches N1˜N8 include NMOS transistors. The phase change memory device includes additional bit line discharge switches N1˜N8 outside the cell array CA. As a result, the conventional memory device must include additional switch regions in order to provide a discharge path of the bit line, which results in a greater overall size of the device.